Usually after the manufacturing process of an array substrate, tests need to be conducted by means of at least one electrical testing instrument (e.g. an ArrayTester) to determine the yield rate of the manufacturing process and the rates for various defects, and so on.
A typical testing process as such is as follows: the array substrate is contacted with a probe of the test instruments, and a test signal is loaded onto at least one test line of the array substrate to thereby conduct the test. Herein the test line is specifically designed for the test during a designing stage of the whole array substrate.
In a subsequent process after the testing, a portion of the test line that is outside a cutting line is typically cut off via a cutting process, and only a portion of the test line that is inside the cutting line is remained. The array substrate formed by the cutting process is illustrated in FIG. 1.
After completing the manufacturing of the array substrate, typically an 8 KV anti-electrostatic test is conducted over the array substrate, which typically involves using an electrostatic gun to discharge to a designated region.
The test line is generally located at a testing region at an edge of the panel. Because the test line is exposed at a cross-section formed after the cutting process, it cannot be completely insulated.
As such, during the anti-electrostatic testing process, the electrostatic charges can enter into the panel through the cross-section of the test line and then discharge inside the internal circuit of the panel, which can in turn cause poor electrostatic discharge (ESD), resulting in a damage to the internal circuit and causing an abnormal display.
In order to address the issues as described above, it is conventionally designed such that the test line is configured to have a post-cutting cross-section arranged at a position as far as possible from the testing region.
However, due to the current trend for narrower bezels and the correspondingly increasing complexity of circuits in current display panels, there is less and less margin that allows for the configuration of the test line in the array substrates, and as such, the conventional strategy of separation is not able to sufficiently address the anti-electrostatic needs.